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| ? 2009 microchip technology inc. ds22226a-page 1 mcp3426/7/8 features 16-bit ? adc with differential inputs: - 2 channels: mcp3426 and mcp3427 - 4 channels: mcp3428 differential input full scale range: -v ref to +v ref self calibration of internal offset and gain per each conversion on-board voltage reference (v ref ): - accuracy: 2.048v 0.05% - drift: 15 ppm/c on-board programmable gain amplifier (pga): - gains of 1,2, 4 or 8 inl: 10 ppm of full scale range programmable data rate options: - 15 sps (16 bits) - 60 sps (14 bits) - 240 sps (12 bits) one-shot or continuous conversion options low current consumption (v dd = 3v): - continuous conversion: 135 a typical - one-shot conversion with 1 sps: - 9 a typical for 16 bit mode - 2.25 a typical for 14 bit mode - 0.56 a typical for 12 bit mode on-board oscillator i 2 c ? interface: - standard, fast and high speed modes - user configurable two external address selection pins for mcp3427 and mcp3428 single supply operation: 2.7v to 5.5v extended temperature range: -40c to +125c typical applications portable instrumentation and consumer goods temperature sensing with rtd, thermistor, and thermocouple bridge sensing for pressure, strain, and force weigh scales and battery fuel gauges factory automation equipment description the mcp3426, mcp3427 and mcp3428 devices (mcp3426/7/8) are the low noise and high accuracy 16 bit delta-sigma analog-to-digital ( ? a/d) con- verter family members of the mcp342x series from microchip technology inc. these devices can convert analog inputs to digital codes with up to 16 bits of reso- lution. the mcp3426 and mcp3427 devices have two differential input channels and the mcp3428 has four differential input channels. all electrical properties of these three devices are the same except the differences in the number of input channels and i 2 c address bit selection options. these devices can output analog-to-digital conversion results at rates of 15 (16-bit mode), 60 (14-bit mode), or 240 (12-bit mode) samples per second depending on the user controllable configuration bit settings using the two-wire i 2 c serial interface. during each conversion, the device calibrates offset and gain errors automatically. this provides accurate conversion results from conversion to conversion over variations in temperature and power supply fluctuation. the device has an on-board 2.048v reference voltage, which enables an input range of 2.048v differentially (full scale range = 4.096/pga). the user can select t he gain of the on-board programmable gain amplifier (pga) using the configuration register bits (gain of x1, x2, x4, or x8). this allows the mcp3426/7/8 devices to convert a very weak input signal with high resolution. the mcp3426/7/8 devices have two conversion modes: (a) one-shot conversion mode and (b) continuous conversion mode. in the one-shot conversion mode, the device performs a single conversion and enters a low current standby (shutdown) mode automatically until it receives another conversion command. this reduces current consumption greatly during idle periods. in continuous conversion mode, the conversion takes place continuously at the configured conversion speed. the device updates its output buffer with the most recent conversion data. the devices operate from a single 2.7v to 5.5v power supply and have a two-wire i 2 c compatible serial interface for a standard (100 khz), fast (400 khz), or high-speed (3.4 mhz) mode. 16-bit, multi-channel ? analog-to-digital converter with i 2 c? interface and on-board reference downloaded from: http:///
mcp3426/7/8 ds22226a-page 2 ? 2009 microchip technology inc. the i 2 c address bits for the mcp3427 and mcp3428 are selected by using two external i 2 c address selection pins (adr0 and adr1). the user can configure the device to one of eight available addresses by connecting these two address selection pins to v dd , v ss or float. the i 2 c address bits of the mcp3426 are programmed at the factory during production. the mcp3426 is available in 8-pin soic, dfn, and msop packages. the mcp3427 is available in 10-pin dfn, and msop packages. the mcp3428 is available in 14-pin soic and tssop packages. package types mcp3426 functional block diagram 45 6 9 ch2- v ss ch3+ adr1 adr0 3 12 ch2+ ch3- 2 13 ch1- ch4+ 1 14 ch1+ ch4- 7 8 sda scl v dd mcp3428 1110 soic, tssop 23 4 7 8 9 ch1- v dd sda adr0 v ss scl 1 10 ch1+ adr1 5 6 ch2- ch2+ mcp3427 23 4 5 6 7 ch1- v dd sda ch2+ v ss scl 1 8 ch1+ ch2- mcp3426 msop, soic msop mcp3426 2x3 dfn * v dd ch1- sda ch2+v ss 1 2 3 4 8 7 6 5 scl ch2- ch1+ * includes exposed thermal pad (ep); see table 3-1 . ep 9 mcp3427 3x3 dfn * v ss ch1- ch2+ adr0 scl 1 2 3 4 10 9 8 7 sda adr1 ch1+ ep 11 ch2- 5 6 v dd v ss v dd pga scl sda mux i 2 c interface gain = 1, 2, 4, or 8 voltage reference clock (2.048v) v ref ? adc converter oscillator mcp3426 ch1+ch1- ch2+ ch2- downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 3 mcp3426/7/8 mcp3427 functional block diagram mcp3428 functional block diagram v ss v dd ch1+ ch1- pga scl sda mux i 2 c interface gain = 1, 2, 4, or 8 adr1 adr0 ch2+ ch2- voltage reference clock (2.048v) v ref ? adc converter oscillator mcp3427 v ss v dd ch1+ ch1- pga scl sda mux i 2 c interface gain = 1, 2, 4, or 8 adr1 adr0 ch2+ch2- ch3+ ch3- ch4+ ch4- voltage reference clock (2.048v) v ref ? adc converter oscillator mcp3428 downloaded from: http:/// mcp3426/7/8 ds22226a-page 4 ? 2009 microchip technology inc. notes: downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 5 mcp3426/7/8 1.0 electrical characteristics absolute maximum ratings? v dd ...................................................................................7.0v all inputs and outputs ............. ..........v ss C0.4v to v dd +0.4v differential input voltage ...................................... |v dd - v ss | output short circuit current ................................ continuous current at input pins ....................................................2 ma current at output and supply pins ............................10 ma storage temperature ....................................-65c to +150c ambient temp. with power applied ...............-55c to +125c esd protection on all pins ................ 6kv hbm, 400v mm maximum junction temperature (t j ). .........................+150c ?notice: stresses above those listed under maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability . electrical characteristics electrical specifications: unless otherwise specified, all parameters apply for t a = -40c to +85c, v dd = +5.0v, v ss = 0v, chn+ = chn- = v ref /2, v incom = v ref /2. all ppm units use 2*v ref as differential full scale range. parameters sym min typ max units conditions analog inputs differential full scale input voltage range fsr 2.048/pga v v in = [chn+ - chn-] maximum input voltage range v ss -0.3 v dd +0.3 v (note 1) differential input impedance z ind (f) 2.25/pga m during normal mode operation (note 2) common mode input impedance z inc (f) 25 m pga = 1, 2, 4, 8 system performance resolution and no missing codes (effective number of bits) (note 3) 12 bits dr = 240 sps 14 bits dr = 60 sps 16 bits dr = 15 sps data rate (note 4) dr 176 240 328 sps 12 bits mode 44 60 82 sps 14 bits mode 11 15 20.5 sps 16 bits mode output noise 2.5 v rms t a = +25c, dr =15 sps, pga = 1, v in + = v in - = gnd integral non-linearity inl 10 ppm of fsr dr = 15 sps (note 5) internal reference voltage v ref 2 . 0 4 8 v gain error (note 6) 0.1 % pga = 1, dr = 15 sps pga gain error match (note 6) 0.1 % between any 2 pga settings gain error drift ( note 6 ) 15 ppm/c pga=1, dr=15 sps note 1: any input voltage below or greater than this voltage causes leakage current through the esd diodes at the input pins. this parameter is ensured by characterization and not 100% tested. 2: this input impedance is due to 3.2 pf internal input sampling capacitor. 3: this parameter is ensured by design and not 100% tested. 4: the total conversion speed includes aut o-calibration of offset and gain. 5: inl is the difference between the endpoints line and the measured code at the center of the quantization band. 6: includes all errors from on-board pga and v ref . 7: this parameter is ensured by characterization and not 100% tested. 8: mcp3427 and mcp3428 only. 9: addr_float voltage is applied at address pin. 10: no voltage is applied at address pin (left floating). downloaded from: http:/// mcp3426/7/8 ds22226a-page 6 ? 2009 microchip technology inc. offset error v os 30 v pga = 1 dr = 15 sps offset drift vs. temperature 50 nv/c common-mode rejection 105 db at dc and pga =1, 110 db at dc and pga =8, t a = +25c gain vs. v dd 5 ppm/v t a = +25c, v dd = 2.7v to 5.5v, pga = 1 power supply rejection at dc input 100 db t a = +25c, v dd = 2.7v to 5.5v, pga = 1 power requirements voltage range v dd 2.7 5.5 v supply current during conversion i dda 145 180 a v dd = 5.0v 135 a v dd = 3.0v supply current during standby mode i dds 0 . 3 1 a v dd = 5.0v i 2 c digital inputs and digital outputs high level input voltage v ih 0.7v dd v dd v at sda and scl pins low level input voltage v il 0.3v dd v at sda and scl pins low level output voltage v ol 0 . 4v i ol = 3 ma hysteresis of schmidt trigger for inputs (note 7) v hyst 0.05v dd v f scl = 100 khz supply current when i 2 c bus line is active i ddb 10 a device is in standby mode while i 2 c bus is active input leakage current i ilh 1 a v ih = 5.5v i ill -1 a v il = gnd logic status of i 2 c address pins (note 8) adr0 and adr1 pins addr_low v ss 0 . 2 v dd v the device reads logic low. adr0 and adr1 pins addr_high 0.75v dd v dd v the device reads logic high. adr0 and adr1 pins addr_float 0.35v dd 0 . 6 v dd v read pin voltage if voltage is applied to the address pin. (note 9) v dd /2 device outputs float output voltage (v dd /2) on the address pin, if left floating. (note 10) pin capacitance and i 2 c bus capacitance pin capacitance c pin 4 1 0p f i 2 c bus capacitance c b 4 0 0p f electrical character istics (continued) electrical specifications: unless otherwise specified, all parameters apply for t a = -40c to +85c, v dd = +5.0v, v ss = 0v, chn+ = chn- = v ref /2, v incom = v ref /2. all ppm units use 2*v ref as differential full scale range. parameters sym min typ max units conditions note 1: any input voltage below or greater than this voltage causes leakage current through the esd diodes at the input pins. this parameter is ensured by characterization and not 100% tested. 2: this input impedance is due to 3.2 pf internal input sampling capacitor. 3: this parameter is ensured by design and not 100% tested. 4: the total conversion speed includes aut o-calibration of offset and gain. 5: inl is the difference between the endpoints line and the measured code at the center of the quantization band. 6: includes all errors from on-board pga and v ref . 7: this parameter is ensured by characterization and not 100% tested. 8: mcp3427 and mcp3428 only. 9: addr_float voltage is applied at address pin. 10: no voltage is applied at address pin (left floating). downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 7 mcp3426/7/8 temperature characteristics electrical specifications: unless otherwise indicated, t a = -40c to +125c, v dd = +5.0v, v ss = 0v. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 +85 c operating temperature range t a -40 +125 c storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 8l-dfn (2x3) ja 8 4 . 5 c / w thermal resistance, 8l-msop ja 2 1 1 c / w thermal resistance, 8l-soic ja 149.5 c/w thermal resistance, 10l-dfn (3x3) ja 5 7 c / w thermal resistance, 10l-msop ja 202 c/w thermal resistance, 14l-soic ja 120 c/w thermal resistance, 14l-tssop ja 100 c/w downloaded from: http:/// mcp3426/7/8 ds22226a-page 8 ? 2009 microchip technology inc. notes: downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 9 mcp3426/7/8 2.0 typical performance curves note: unless otherwise indicated, t a = -40c to +85c, v dd = +5.0v, v ss = 0v, chn+ = chn- = v ref /2, v incom = v ref /2. figure 2-1: inl vs. supply voltage (v dd ). figure 2-2: inl vs. temperature. figure 2-3: offset error vs. temperature. figure 2-4: output noise vs. input voltage. figure 2-5: total error vs. input voltage. figure 2-6: gain error vs. temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0 0.001 0.002 0.003 0.004 0.005 2 . 533 . 544 . 555 . 5 v dd (v) integral nonlinearity (% fsr) pga = 1 pga = 4 pga = 8 pga = 2 0 0.001 0.002 0.003 0.004 0.005 -60 -40 -20 0 20 40 60 80 100 120 140 temperature ( o c) inl (% fsr) 2.7v 5v -25 -20 -15 -10 -5 0 5 10 15 20 -40 -20 0 20 40 60 80 100 120 140 temperature ( o c) offset error (v) v dd = 5v pga = 1 pga = 2 pga = 4 pga = 8 0 2 4 6 8 10 12 -100 -75 -50 -25 0 25 50 75 100 input signal (% of fsr) output noise (v, rms) pga = 1 pga = 8 pga = 4 pga = 2 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -100 -75 -50 -25 0 25 50 75 100 input voltage (% of full-scale) total error (mv) pga = 1 pga = 8 pga = 4 pga = 2 t a = +25c -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) gain error (% of fsr) pga = 1 pga = 2 pga = 4 pga = 8 downloaded from: http:/// mcp3426/7/8 ds22226a-page 10 ? 2009 microchip technology inc. note: unless otherwise indicated, t a = -40c to +85c, v dd = +5.0v, v ss = 0v, chn+ = chn- = v ref /2, v incom = v ref /2. figure 2-7: i dda vs. temperature. figure 2-8: i dds vs. temperature. figure 2-9: i ddb vs. temperature. figure 2-10: oscillator drift vs. temperature. figure 2-11: frequency response. 60 80 100 120 140 160 180 200 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) i dda (a) v dd = 5.5v v dd = 5.0v v dd = 2.7v 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) i dds (a) v dd = 2.7v v dd = 5.0v v dd = 5.5v 0 2 4 6 8 10 12 14 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) i ddb (a) v dd = 5.5v v dd = 5.0v v dd = 4.5v v dd = 2.7v -1 0 1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) oscillator drift (%) v dd = 5.0v v dd = 2.7v -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.1 1 10 100 1000 10000 input signal frequency (hz) magnitude (db) data rate = 15 sps 10k 1k downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 11 mcp3426/7/8 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 analog inputs (chn+, chn-) chn+ and chn- are differential input pins for channel n. the user can also connect chn- pin to v ss for a single-ended operation. see figure 6-4 for differential and single-ended connection examples. the maximum voltage range on each differential input pin is from v ss -0.3v to v dd +0.3v. any voltage below or above this range will cause leakage currents through the electrostatic discharge (esd) diodes at the input pins. this esd current can cause unexpected performance of the device. the input volt age at the input pins should be within the specified operating range defined in section 1.0 electrical characteristics and section 4.0 description of device operation . see section 4.5 input voltage range for more details of the input voltage range. figure 3-1 shows the input structure of the device. the device uses a switched capacitor input stage at the front end. c pin is the package pin capacitance and typically about 4 pf. d 1 and d 2 are the esd diodes. c sample is the differential input sampling capacitor. 3.2 supply voltage (v dd , v ss ) v dd is the power supply pin for the device. this pin requires an appropriate bypass ceramic capacitor of about 0.1 f to ground to attenuate high frequency noise presented in application circuit board. an additional 10 f capacitor (tantalum) in parallel is also recommended to further attenuate current spike noises. the supply voltage (v dd ) must be maintained in the 2.7v to 5.5v ran ge for specified operation. v ss is the ground pin and the current return path of the device. the user must connect the v ss pin to a ground plane through a low impedance connection. if an analog ground path is available in the application pcb (printed circuit board), it is highly recommended that the v ss pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. mcp3426 mcp3427 mcp3428 sym function dfn msop, soic dfn msop soic, tssop 1 1 1 1 1 ch1+ positive differential analog input pin of channel 1 2 2 2 2 2 ch1- negative differential analog input pin of channel 1 7 7 4 4 3 ch2+ positive differential analog input pin of channel 2 8 8 5 5 4 ch2- negative differential analog input pin of channel 2 6633 5 v ss ground pin 3366 6 v dd positive supply voltage pin 4 4 7 7 7 sda bidirectional serial data pin of the i 2 c interface 5 5 8 8 8 scl serial clock pin of the i 2 c interface 9 9 9 a d r 0i 2 c address selection pin. see section 5.3.2. 10 10 10 adr1 i 2 c address selection pin. see section 5.3.2. 11 ch3+ positive differential analog input pin of channel 3 12 ch3- negative differential analog input pin of channel 3 13 ch4+ positive differential analog input pin of channel 4 14 ch4- negative differential analog input pin of channel 4 9 11 ep exposed thermal pad (ep); must be connected to v ss downloaded from: http:/// mcp3426/7/8 ds22226a-page 12 ? 2009 microchip technology inc. figure 3-1: equivalent analog input circuit. 3.3 serial clock pin (scl) scl is the serial clock pin of the i 2 c interface. the device acts only as a slave and the scl pin accepts only external serial clocks. the input data from the master device is shifted into the sda pin on the rising edges of the scl clock an d output from the slave device occurs at the falling edges of the scl clock. the scl pin is an open-drain n-channel driver. therefore, it needs a pull-up resistor from the v dd line to the scl pin. refer to section 5.3 i 2 c serial communications for more details on i 2 c serial interface communication. 3.4 serial data pin (sda) sda is the serial data pin of the i 2 c interface. the sda pin is used for input and output data. in read mode, the conversion result is read fr om the sda pin (output). in write mode, the device config uration bits are written (input) though the sda pin. the sda pin is an open-drain n-channel driver. therefore, it needs a pull-up resistor from the v dd line to the sda pin. except for start and stop conditions, the data on the sda pin must be stable during the high period of the clock. the high or low state of the sda pin can only change when the clock signal on the scl pin is low. refer to section 5.3 i 2 c serial communications for more details on i 2 c serial interface communication. the typical range of the pull-up resistor value for scl and sda is from 5 k to 10 k for standard (100 khz) and fast (400 khz) modes, and less than 1 k for high speed mode (3.4 mhz). 3.5 exposed thermal pad (ep) there is an internal electrical connection between the exposed thermal pad (ep) and the v ss pin; they must be connected to the same potential on the printed circuit board (pcb). c pin v r ss chn 4pf v t = 0.6v v t = 0.6v i leakage samplingswitch ss r s c sample (3.2 pf) v dd (~ 1 na) l egend v = signal source i leakage = leakage current at analog pin r ss = source impedance ss = sampling switch chn = analog input pin r s = sampling switch resistor c pin = input pin capacitance c sample = sample capacitance v t = threshold voltage d1, d2 = esd protection diode d 1 d 2 v ss downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 13 mcp3426/7/8 4.0 description of device operation 4.1 general overview the mcp3426/7/8 devices are differential multi-channel low-power, 16-bit delta-sigma a/d converters with an i 2 c serial interface. the devices contain an input channel selection multiplexer (mux), a programmable gain amplifier (pga), an on-board voltage reference (2.048v), and an internal oscillator. when the device powers up (por is set), it automatically resets the configuration bits to default settings. 4.1.1 device default settings are: conversion bit resolution: 12 bits (240 sps) input channel: channel 1 pga gain setting: x1 continuous conversion once the device is powe red-up, the user can reprogram the configuration bits using i 2 c serial interface any time. the confi guration bits are stored in the volatile memory. 4.1.2 user selectabl e options are: conversion bit resolution: 12, 14, or 16 bits input channel selection: ch1, ch2, ch3, or ch4. pga gain selection: x1, x2, x4, or x8 continuous or one-shot conversion in the continuous conversion mode, the device converts the inputs continu ously. while in the one-shot conversion mode, the device converts the input one time and stays in the low-power standby mode until it receives another command for a new conversion. during the standby mode, the device consumes less than 1 a maximum. 4.2 power-on-reset (por) the device contains an internal power-on-reset (por) circuit that monito rs power supply voltage (v dd ) during operation. this circuit ensures correct device start-up at system power-up and power-down events. the device resets all configuration register bits to default settings as soon as the por is set. the por has built-in hysteresis and a timer to give a high degree of immunity to potential ripples and noises on the power supply. a 0.1 f decoupling capacitor should be mounted as close as possible to the v dd pin for additional transient immunity. the threshold voltage is set at 2.2v with a tolerance of approximately 5%. if the supply voltage falls below this threshold, the device will be held in a reset condition. the typical hysteresis value is approximately 200 mv. the por circuit is shut down during the low-power standby mode. once a power-up event has occurred, the device requires additional delay time (approximately 300 s) before a conversion takes place. during this time, all internal analog circuitries are settled before the first conversion occurs. figure 4-1 illustrates the conditions for power-up and power-down events under typical start-up conditions. figure 4-1: por operation. 4.3 internal voltage reference the device contains an on-board 2.048v voltage reference. this reference vo ltage is for internal use only and not directly meas urable. the specification of the reference voltage is part of the devices gain and drift specifications. therefore, there is no separate specification for the on-board reference. 4.4 analog input channels the user can select the input channel using the configuration register bits. each channel can be used for differential or single-ended input. each input channel has a switched capacitor input structure. the internal sa mpling capacitor (3.2 pf for pga = 1) is charged and discharged to process a conversion. the charging and discharging of the input sampling capacitor creates dynamic input currents at each input pin. the current is a function of the differential input voltages, and inversely proportional to the internal sampling capacitance, sampling frequency, and pga setting. v dd 2.2v 2.0v 300 s reset start-up normal operation reset time downloaded from: http:/// mcp3426/7/8 ds22226a-page 14 ? 2009 microchip technology inc. 4.5 input voltage range the differential (v in ) and common mode voltage (v incom ) at the input pins wit hout considering pga setting are defined by: the input signal levels are amplified by the internal programmable gain amplifier (pga) at the front end of the ? modulator. the user needs to consider two conditions for the input voltage range: (a) differential input voltage range and (b) absolute maximum input voltage range. 4.5.1 differential input voltage range the device performs conversions using its internal reference voltage (v ref = 2.048v). therefore, the absolute value of the differential input voltage (v in ), with pga setting is included, needs to be less than the internal reference voltage. the device will output saturated output codes (all 0s or all 1s except sign bit) if the absolute value of the input voltage (v in ), with pga setting is included, is greater than the internal reference voltage (v ref = 2.048v). the input full scale voltage range is given by: equation 4-1: if the input voltage level is greater than the above limit, the user can use a voltage divider and bring down the input level within the full scale range. see figure 6-7 for more details of the input voltage divider circuit. 4.5.2 absolute maximum input voltage range the input voltage at each input pin must be less than the following absolute maximum input voltage limits: input voltage < v dd +0.3v input voltage > v ss -0.3v any input voltage outside this range can turn on the input esd protection diodes, and result in input leakage current, causing conversion errors, or permanently damage the device. care must be taken in setting the input voltage ranges so that the input voltage does not exceed the absolute maximum input voltage range. 4.6 input impedance the device uses a switched-capacitor input stage using a 3.2 pf sampling capacitor. this capacitor is switched (charged and discharged) at a rate of the sampling frequency that is generated by on-board clock. the differential input impedance varies with the pga settings. the typical differential input impedance during a normal mode operation is given by: since the sampling capacitor is only switching to the input pins during a conver sion process, the above input impedance is only valid during conversion periods. in a low power standby mode, the above impedance is not presented at the input pins. therefore, only a leakage current due to esd diode is presented at the input pins. the conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. the source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. therefore, a large input so urce impedance connected to the input pins can deg rade the system performance, such as offset, gain, and integral non-linearity (inl) errors. ideally, the input source impedance should be zero. this can be achievable by using an operational amplifier with a closed-loop output impedance of tens of ohms. 4.7 aliasing and anti-aliasing filter aliasing occurs when the input signal contains time-varying signal components with frequency greater than half the sample rate. in the aliasing conditions, the device can output unexpec ted output codes. for applications that are operating in electrical noise environments, the time-varying signal noise or high frequency interference components can be easily added to the input signals and cause aliasing. although the device has an internal firs t order sinc filter, the filter response ( figure 2-11 ) may not give enough attenuation to all aliasing signal components. to avoid the aliasing, an external anti-aliasing filter, which can be accomplished with a simple rc low-pass filter, is typically used at the input pins. the low-pass filter cuts off the high frequency noise components and provides a band-limited input signal to the input pins. 4.8 self-calibration the device performs a self-calibration of offset and gain for each conversion. this provides reliable conversion results from conv ersion-to-conversion over variations in temperature as well as power supply fluctuations. v in chn+ () chn- () C = v incom chn+ () chn- () + 2 ----------------------------------------------- = where: n = nth input channel (n=1, 2, 3, or 4) where: v in = chn+ - chn- v ref = 2.048v v ref C v in pga ? () v ref 1lsb C () ? z in (f) = 2.25 m /pga downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 15 mcp3426/7/8 4.9 digital output codes and conversion to real values 4.9.1 digital output code from device the digital output code is proportional to the input voltage and pga settings. the output data format is a binary twos complement. with this code scheme, the msb can be considered a sign indicator. when the msb is a logic 0 , the input is positive. when the msb is a logic 1 , the input is negativ e. the following is an example of the output code: (a) for a negative full scale input voltage: 100...000 example: (chn+ - chn-) pga = -2.048v (b) for a zero differential input voltage: 000...000 example: (chn+ - chn-) = 0 (c) for a positive full scale input voltage: 011...111 example: (chn+ - chn-) pga = 2.048v the msb (sign bit) is always transmitted first through the i 2 c serial data line. the resolution for each conversion is 16, 14, or 12 bits depending on the conversion rate selection bit settings by the user. the output codes will not ro ll-over even if the input voltage exceeds the maximum input range. in this case, the code will be locked at 0111...11 for all voltages greater than (v ref - 1 lsb)/pga and 1000...00 for voltages less than -v ref /pga. table 4-2 shows an example of output codes of various input levels for 16-bit conversion mode. table 4-3 shows an example of minimum and maximum output codes for each conversion rate option. the number of output code is given by: equation 4-2: the lsb of the data conversion is given by: equation 4-3: table 4-1 shows the lsb size of each conversion rate setting. the measured unknown input voltage is obtained by multiplying the output codes with lsb. see the following section for the input voltage calculation using the output codes. table 4-1: resolution settings vs. lsb table 4-2: example of output code for 16 bits (note 1, note 2) table 4-3: minimum and maximum output codes (note) number of output code = maximum code 1 + () pga chn + chn - C () 2.048v ---------------------------------------- - = where: see ta b l e 4 - 3 for maximum code lsb 2 v ref 2 n --------------------- - 2 2.048 v 2 n -------------------------- == where: n = resolution, which is programmed in the configuration register: 12, 14, or 16. resolution setting lsb 12 bits 1 mv 14 bits 250 v 16 bits 62.5 v input voltage: [chn+ - chn-] pga digital output code v ref 0111111111111111 v ref - 1 lsb 0111111111111111 2lsb 0000000000000010 1lsb 0000000000000001 0 0000000000000000 -1 lsb 1111111111111111 -2 lsb 1111111111111110 - v ref 1000000000000000 < -v ref 1000000000000000 note 1: msb is a sign indicator: 0 : positive input (chn+ > chn-) 1 : negative input (chn+ < chn-) 2: output data format is binary twos complement. resolution setting data rate minimum code maximum code 12 240 sps -2048 2047 14 60 sps -8192 8191 16 15 sps -32768 32767 note: maximum n-bit code = 2 n-1 - 1 minimum n-bit code = -1 x 2 n-1 downloaded from: http:/// mcp3426/7/8 ds22226a-page 16 ? 2009 microchip technology inc. 4.9.2 converting the device output code to input signal voltage when the user gets the digital output codes from the device as described in section 4.9.1 digital output code from device , the next step is converting the digital output codes to a measured input voltage. equation 4-4 shows an example of converting the output codes to its corresponding input voltage. if the sign indicator bit (msb) is 0 , the input voltage is obtained by multiplying the output code with the lsb and divided by the pga setting. if the sign indicator bit (msb) is 1 , the output code needs to be converted to twos complement before multiplied by lsb and divided by the pga setting. table 4-4 shows an example of converting the device output codes to input voltage. equation 4-4: converting output codes to input voltage table 4-4: example of converting output code to voltage (with 16 bit setting) if msb = 0 (positive output code): if msb = 1 (negative output code): where: lsb = see table 4-1 2s complement = 1s complement + 1 input voltage (output code) lsb pga ----------- - ? = input voltage (2 s complement of output code) lsb pga ------------ ? = input voltage [chn+ - chn-] pga] digital output code msb example of converting output codes to input voltage v ref 0111111111111111 0 (2 14 +2 13 +2 12 +2 11 +2 10 +2 9 +2 8 +2 7 +2 6 +2 5 +2 4 +2 3 +2 2 +2 1 +2 0 )x lsb(62.5 v)/pga = 2.048 (v) for pga = 1 v ref - 1 lsb 0111111111111111 0 (2 14 +2 13 +2 12 +2 11 +2 10 +2 9 +2 8 +2 7 +2 6 +2 5 +2 4 +2 3 +2 2 +2 1 +2 0 )x lsb(62.5 v)/pga = 2.048 (v) for pga = 1 2lsb 0000000000000010 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+2 1 +0)x lsb(62.5 v)/pga = 125 ( v) for pga = 1 1lsb 0000000000000001 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+0+2 0 )x lsb(62.5 v)/pga = 62.5 ( v)for pga = 1 0 0000000000000000 0 (0+0+0+0+0+0+0+0+0+0+0+0+0+0+0)x lsb(62.5 v)/pga = 0 v (v) for pga = 1 -1 lsb 1111111111111111 1 -(0+0+0+0+0+0+0+0+0+0+0+0+0+0+2 0 )x lsb(62.5 v)/ pga = - 62.5 ( v)for pga = 1 -2 lsb 1111111111111110 1 -(0+0+0+0+0+0+0+0+0+0+0+0+0+2 1 +0)x lsb(62.5 v)/ pga = - 125 ( v)for pga = 1 - v ref 1000000000000000 1 -(2 15 +0+0+0+0+0+0+0+0+0+0+0+0+0+0) x lsb(62.5 v)/ pga = - 2.048 (v) for pga = 1 -v ref 1000000000000000 1 -(2 15 +0+0+0+0+0+0+0+0+0+0+0+0+0+0) x lsb(62.5 v)/ pga = - 2.048 (v) for pga = 1 note: msb = sign bit ( 1 : -, 0 : +) downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 17 mcp3426/7/8 5.0 using the devices 5.1 operating modes the user operates the device by setting up the device configuration register us ing a write command (see figure 5-3 ) and reads the conversion data using a read command (see figure 5-4 ). the device operates in two modes: (a) continuous conversion mode or (b) one-shot conversion mode (single conversion). this mode selection is made by setting the o /c bit in the configuration register. refer to section 5.2 configuration register for more information. 5.1.1 continuous conversion mode (o /c bit = 1 ) the device performs a continuous conversion if the o /c bit is set to logic high. once the conversion is completed, rdy bit is toggled to 0 and the result is placed at the output data register. the device immediately begins another conversion and overwrites the output data register with the most recent result. the device clears the data ready flag (rdy bit = 0 ) when the conversion is completed. the device sets the ready flag bit (rdy bit = 1 ), if the latest conversion result has been read by the master. when writing configuration register: - setting rdy bit in continuous mode does not affect anything. when reading conversion data: - rdy bit = 0 means the latest conversion result is ready. - rdy bit = 1 means the conversion result is not updated since the last reading. a new conversion is under processing and the rdy bit will be cleared when the new conversion result is ready. 5.1.2 one-shot conversion mode (o /c bit = 0 ) once the one-shot conversion (single conversion) mode is selected, the device performs only one conversion, updates the output data register, clears the data ready flag (rdy = 0 ), and then enters a low power standby mode. a new one-shot conversion is started again when the device receives a new write command with rdy = 1 . when writing configuration register: - the rdy bit needs to be set to begin a new conversion in one-shot mode. when reading conversion data: - rdy bit = 0 means the latest conversion result is ready. - rdy bit = 1 means the conversion result is not updated since the last reading. a new conversion is under processing and the rdy bit will be cleared when the new conversion is done. this one-shot conversion mode is highly recommended for low power operating applications where the conversion result is needed by request on demand. during the low current standby mode, the device consumes less than 1 a maximum (or 300 na typical). for example, if the user collects 16-bit conversion data once a second in one-shot conversion mode, the device draws only about one- fifteenth of the operating currents for the continuous conversion mode. in this example, the device consumes approximately 9 a (135 a / 15 sps = 9 a), when the device performs only one conversion per second (1 sps) in 16-bit conversion mode with 3v power supply. downloaded from: http:/// mcp3426/7/8 ds22226a-page 18 ? 2009 microchip technology inc. 5.2 configuration register the device has an 8-bit wide configuration register to select for: input channel, conversion mode, conversion rate, and pga gain. this register allows the user to change the operating conditi on of the device and check the status of the device operation. the user can rewrite the configuration byte any time during the device operation. register 5-1 shows the configuration register bits. register 5-1: configuration register r/w-1 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 rdy c1 c0 o /c s1 s0 g1 g0 1 * 0 * 0 * 1 * 0 * 0 * 0 * 0 * bit 7 bit 0 * default configuration after power-on reset legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 -n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown bit 7 rdy : ready bit this bit is the data ready flag. in read mode, this bit indicates if the output register has been updated with a latest conversion result. in one-sh ot conversion mode, writing this bit to 1 initiates a new conversion. reading rdy bit with the read command: 1 = output register has not been updated. 0 = output register has been updated with the latest conversion result. writing rdy bit with the write command: continuous conversion mode: no effect one-shot conversion mode: 1 = initiate a new conversion. 0 = no effect. bit 6-5 c1-c0: channel selection bits 00 = select channel 1 (default) 01 = select channel 2 10 = select channel 3 (mcp3428 only, treated as 00 by the mcp3426/mcp3427) 11 = select channel 4 (mcp3428 only, treated as 01 by the mcp3426/mcp3427) bit 4 o /c: conversion mode bit 1 = continuous conversion mode (default) . the device performs data conversions continuously. 0 = one-shot conversion mode. the device performs a single conversion and enters a low power standby mode until it receives ano ther write or read command. bit 3-2 s1-s0: sample rate selection bit 00 = 240 sps (12 bits) (default) 01 = 60 sps (14 bits) 10 = 15 sps (16 bits) bit 1-0 g1-g0: pga gain selection bits 00 =x1 (default) 01 =x2 10 =x4 11 =x8 downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 19 mcp3426/7/8 if the configuration byte is read repeatedly by clocking continuously after reading the data bytes (i.e., after the 4th byte in the 16-bit conver sion mode), the state of the rdy bit indicates whether the device is ready with new conversion result. when the master finds the rdy bit is cleared, it can send a not-acknowledge (nak) bit and a stop bit to exit the current read operation and send a new read command for the latest conversion data. once the conversion data has been read, the ready bit toggles to 1 until the next new conversion data is ready. the conversion data in the output register is overwritten every time a ne w conversion is completed. figure 5-3 shows an example of writing configuration register, and figure 5-4 shows an example of reading conversion data. the user c an rewrite the configuration byte any time for a new setting. ta b l e 5 - 1 and ta b l e 5 - 2 show the examples of the configuration bit operation. 5.3 i 2 c serial communications the device communicates with the master (microcontroller) through a serial i 2 c (inter-integrated circuit) interface and support standard (100 kbits/sec), fast (400 kbits/sec) and high-speed (3.4 mbits/sec) modes. the serial i 2 c is a bidirectional 2-wire data bus communication protocol using open-drain scl and sda lines. the device can only be addressed as a slave. once addressed, it can receive c onfiguration bits with a write command or transmit the latest conversion results with a read command. the serial clock pin (scl) is an input only and the serial data pin (sda) is bidirectional. the master starts communication by sending a start bit and terminates the commun ication by sending a stop bit. in read mode, the device releases the sda line after receiving nak and stop bits. an example of a hardware connection diagram is shown in figure 6-1 . more details of the i 2 c bus characteristic is described in section 5.6 i 2 c bus characteristics . 5.3.1 i 2 c device addressing the first byte after the start bit is always the address byte of the device, which includes the device code (4 bits), address bits (3 bits), and r/w bit. the device code for the devices is 1101 , which is programmed at the factory. the i 2 c address bits (a2, a1, a0 bits) are as follows: mcp3426: programmed at factory mcp3427 and mcp3428: progammed by the user. it is determined by the logic status of the two external address selection pins on the users application board (adr0 and adr1 pins). the master must know the adr0 and adr1 pin conditions before sending read or write command. see section 5.3.2 device address bits (a2, a1, a0) and address selection pins (mcp3427 and mcp3428) for more details figure 5-1 shows the details of the address byte. the three i 2 c address bits allow up to eight devices on the same i 2 c bus line. the (r/w ) bit determines if the master device wants to read the conversion data or write to the configuration register. if the (r/w ) bit is set (read mode), the device outputs the conversion data in the following clo cks. if the (r/w ) bit is cleared (write mode), the device expects a configuration byte in the following clocks. when the device receives the correct address byte, it outputs an acknowledge bit after the r/w bit. table 5-1: write configuration bits r/w o /c rdy operation 00 0 no effect if all other bits remain the same - operation continues with the previous settings. 00 1 initiate one-shot conversion. 01 0 initiate continuous conversion. 01 1 initiate continuous conversion. table 5-2: read configuration bits r/w o /c rdy operation 10 0 new conversion result in one- shot conversion mode has just been read. the rdy bit remains low until set by a new write command. 10 1 one-shot conversion is in prog- ress. the conversion result is not updated yet. the rdy bit stays high until the current conversion is completed. 11 0 new conversion result in continuous conversion mode has just been read. the rdy bit changes to high after reading the conversion data. 11 1 the conversion result in continuous conversion mode was already read. the next new conversion data is not ready. the rdy bit stays high until a new conversion is completed. downloaded from: http:/// mcp3426/7/8 ds22226a-page 20 ? 2009 microchip technology inc. figure 5-1: address byte. 5.3.2 device address bits (a2, a1, a0) and address selection pins (mcp3427 and mcp3428) the mcp3427 and mcp3428 have two external device address pins (adr1, adr0). these pins can be set to a logic high (or tied to v dd ), low (or tied to v ss ), or left floating (not connected to anything, or tied to v dd /2), these combinations of logic level using the two pins allow eight possible addresses. table 5-3 shows the device address depending on the logic status of the address selection pins. the device samples the logic status of the adr0 and adr1 pins in the following events: (a) device power-up. (b) general call reset (see section 5.4 general call ). (c) general call latch (see section 5.4 general call ). the device samples the logic status (address pins) during the above events, and latches the values until a new latch event occurs. during normal operation (after the address pins are latc hed), the address pins are internally disabled from the rest of the internal circuit. it is recommended to issue a general call reset or general call latch command once after the device has powered up. this will ensure that the device reads the address pins in a stable condition, and avoid latching the address bits while the power supply is ramping up. this might cause inaccurate address pin detection. when the address pin is left floating: when the address pin is left floating, the address pin momentarily outputs a short pulse with an amplitude of about v dd /2 during the latch event. the device also latches this pin voltage at the same time. if the floating pin is connected to a large parasitic capacitance (> 20 pf) or to a long pcb trace, this short floating voltage output can be altered. as a result, the device may not latch the pin correctly. it is strongly recommended to keep the floating pin pad as short as possible in the customer application pcb and minimize the parasitic capacitance to the pin as small as possible (< 20 pf). figure 5-2 shows an example of the latch voltage output at the address pin when the address pin is left floating. the waveform at t he adr0 pin is captured by using an oscilloscope probe with 15 pf of capacitance. the device latches the float ing condition immediately after the general call latch command. figure 5-2: general call latch command and voltage output at address pin left floating (mcp3427 and mcp3428). start bit read/write bit address byte r/w ack 1 1 0 1 a2 a1 a0 device code address bits (note 1) address byte: acknowledge bit address note 1: mcp3427 and mcp3428: configured by the user. see table 5-4 for address bit configurations. 2: mcp3426: programmed at the factory during production. float waveform (output) a t address pin scl sda downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 21 mcp3426/7/8 table 5-3: address bits vs. address selection pins for (mcp3427 and mcp3428 only) (note1,2,3) 5.3.3 writing a configuration byte to the device when the master sends an address byte with the r/w bit low (r/w = 0 ), the device expects one configuration byte following the address. any byte sent after this second byte will be ignored. the user can change the operating mode of the device by writing the configuration register bits. if the device receives a write command with a new configuration setting, the device immediately begins a new conversion and updates the conversion data. figure 5-3: timing diagram for writing to the mcp3426/7/8. i 2 c device address bits logic status of address selection pins a2 a1 a0 adr0 pin adr1 pin 000 0 (addr_low) 0 (addr_low) 001 0 (addr_low) float 010 0 (addr_low) 1 (addr_high) 100 1 (addr_high) 0 (addr_low) 101 1 (addr_high) float 110 1 (addr_high) 1 (addr_high) 011 float 0 (addr_low) 111 float 1 (addr_high) 000 float float note 1: float: (a) leave pin without connecting to anything (left floating), or (b) apply addr_float voltage. 2: the user can tie the pins to v ss or v dd : - tie to v ss for addr_low - tie to v dd for addr_high 3: see addr_low, addr_high, and addr_float parameters in electrical characteristics table . 9 1 9 1 stop bit by 11 0 1a2 a1 a0 r/w ack by mcp3426/7/8 rdy c1 c0 o /c s1 s0 g1 g0 1st byte: 2nd byte: master ack by mcp3426/7/8 address byte configuration byte start bit by master with write command note: C stop bit can be issued any time during writing. C mcp3426/7/8 device code is 1101 (programmed at the factory). C see figure 5-1 for details in address byte. sclsda (a) one-shot mode: 1 (b) continuous mode: not effected downloaded from: http:/// mcp3426/7/8 ds22226a-page 22 ? 2009 microchip technology inc. 5.3.4 reading output codes and configuration byte from the device when the master sends a read command (r/w = 1 ), the device outputs both the conversion data and configuration bytes. each by te consists of 8 bits with one acknowledge (ack) bit. the ack bit after the address byte is issued by the device and the ack bits after each conversion data bytes are issued by the master. when the device receives a read command, it outputs two data bytes followed by a configuration register. in 16-bit conversion mode, the msb (= sign bit) of the first data byte is d15. in 14-bit conversion mode, the first two bits in the first data byte are repeated msb bits and can be ignored, and the 3rd bit (d13) is the msb (=sign bit) of the conversion data. in 12-bit conversion mode, the first four bits are repeated msb bits and can be ignored. the 5th bit (d11) of the byte represents the msb (= sign bit) of the conversion data. table 5-4 summarizes the conversion data output of each conversion mode. the configuration byte follows the output data bytes. the device repeatedly outputs the configuration byte only if the master sends clocks repeatedly after the data bytes. the device terminates the current outputs when it receives a not-acknowledge (nak) with a repeated start or a stop bit at the end of each output byte. it is not required to read the configuration byte. however, the master may read the configuration byte to check the rdy bit condition.the master may continuously send clock (scl) to repeatedly read the configuration byte (to check the rdy bit status). figure 5-4 shows the timing diagram for reading the adc conversion data. table 5-4: output codes of each resolution option conversion option digital output codes 16-bits d15 ~ d8 (1st data byte) - d7 ~ d0 (2nd data byte) - configuration byte. (note 1) 14-bits mmd13d ~ d8 (1st data byte) - d7 ~ d0 (2nd data byte) - configuration byte. (note 2) 12-bits mmmmd11 ~ d8 (1st data byte) - d7 ~ d0 (2nd data byte) - configuration byte. (note 3) note 1: d15 is msb (= sign bit). 2: d13 is msb (= sign bit), m is repeated msb of the data byte. 3: d11 is msb (= sign bit), m is repeated msb of the data byte. downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 23 mcp3426/7/8 figure 5-4: timing diagram for reading from the mcp 3426/7/8 with 12-bit to 16-bit modes. 1 1 0 1 a2 a1 a0 ack by mcp3426/7/8 start bit by master 2nd byte upper data byte ack by master ack by master d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 c 1 c 0 s 1 s 0 g 1 g 0 1st byte mcp3426/7/8 address byte 3rd byte lower data byte 4th byte configuration byte (optional) c 1 c 0 s 1 s 0 g 1 g 0 nak by master stop bit by master (optional) nth repeated byte: configuration byte note: C mcp3426/7/8 device code is 1101 . C see figure 5-1 for details in address byte. C stop bit or nak bit can be issued at the end of each output byte. C in 14 - bit mode: d15 and d14 are repeated msb and can be ignored. C in 12 - bit mode: d15 - d12 are repeated msb and can be ignored. C configuration byte repeats as long as clock is provided after the 4th byte. 9 1 99 1 9 1 9 1 scl sda 9 1 rdy o /c r/w rdy o /c to continue: ack by master to end: nak by master downloaded from: http:/// mcp3426/7/8 ds22226a-page 24 ? 2009 microchip technology inc. 5.4 general call the device acknowledges the general call address (0x00 in the first byte). th e meaning of the general call address is always specified in the second byte. refer to figure 5-5 . the device supports the following three general calls. for more information on the general call, or other i 2 c modes, refer to the phillips i 2 c specification. 5.4.1 general call reset the general call reset occurs if the second byte is 00000110 (06h). at the acknowledgement of this byte, the device will abort current conversion and perform the following tasks: (a) internal reset similar to a power-on-reset (por). all configuration and data register bits are reset to default values. (b) latch the logic status of external address selection pins (adr0 and adr1 pins). 5.4.2 general call latch (mcp3427 and mcp3428) the general call latch occurs if the second byte is 00000100 (04h). the device will latch the logic sta- tus of the external address selection pins (adr0 and adr1 pins), but will not perform a reset. 5.4.3 general call conversion the general call conversion occurs if the second byte is 00001000 (08h). all devices on the bus initiate a conversion simultaneously. when the device receives this command, the configuration will be set to the one-shot conversion mode and a single conversion will be performed. the pga and data rate settings are unchanged with this general call. figure 5-5: general call address format. 5.5 high-speed (hs) mode the i 2 c specification requires that a high-speed mode device must be activated to operate in high-speed mode. this is done by sending a special address byte of 00001xxx following the start bit. the xxx bits are unique to the high-speed (hs) mode master. this byte is referred to as the high-speed (hs) master mode code (hsmmc). the mcp3426/7/8 devices do not acknowledge this byte. however, upon receiving this code, the device switches on its hs mode filters and communicates up to 3.4 mhz on sda and scl bus lines. the device will switch out of the hs mode on the next stop condition. for more information on the hs mode, or other i 2 c modes, refer to the philips i 2 c specification. 5.6 i 2 c bus characteristics the i 2 c specification defines the following bus protocol: data transfer may be initiated only when the bus is not busy during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition accordingly, the following bus conditions have been defined using figure 5-6 . 5.6.1 bus not busy (a) both data and clock lines remain high. 5.6.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 5.6.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations can be ended with a stop condition. 5.6.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is init iated with a start condition and terminated with a stop condition. lsb first byte ack x 0 0 0 0 0 0 0 0 a a xxxxxxx (general call address) second byte note: the i 2 c specification does not allow 00000000 (00h) in the second byte. s s start ack stop downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 25 mcp3426/7/8 5.6.5 acknowledge and non-acknowledge the master (microcontroller) and the slave (mcp3426/ 7/8) use an acknowledge pulse (ack) as a hand shake of communication for each byte. the ninth clock pulse of each byte is used for the acknowledgement. the clock pulse is always provided by the master (microcontroller) and the acknowledgement is issued by the receiving device of the byte (note: the transmitting device must release the sda line during the acknowledge pulse.). the acknowledgement is achieved by pulling-down the sda line low during the 9th clock pulse by the receiving device. during reads, the master (microcontroller) can terminate the current read ope ration by not providing an acknowledge bit (not acknowledge (nak)) on the last byte. in this case , the mcp3426/7/8 devices release the sda line to allow the master (microcontroller) to generate a stop or repeated start condition. the non-acknowledgement (nak) is issued by providing the sda line to high during the 9th clock pulse. figure 5-6: data transfer sequence on i 2 c serial bus. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition downloaded from: http:/// mcp3426/7/8 ds22226a-page 26 ? 2009 microchip technology inc. table 5-5: i 2 c serial timing specifications electrical specifications: unless otherwise specified, all limits are specified for t a = -40 to +85c, v dd = +2.7v to +5.0v, v ss = 0v, chn+ = chn- = v ref /2. parameters sym min typ max units conditions standard mode (100 khz) clock frequency f scl 0 100 khz clock high time t high 4000 ns clock low time t low 4700 ns sda and scl rise time t r 1000 ns from v il to v ih (note 1) sda and scl fall time t f 300 ns from v ih to v il (note 1) start condition hold time t hd:sta 4000 ns after this period, the first clock pulse is generated. repeated start condition setup time t su:sta 4700 ns only relevant for repeated start condition data hold time t hd:dat 0 3450 ns (note 3) data input setup time t su:dat 250 ns stop condition setup time t su:sto 4000 ns output valid from clock t aa 0 3750 ns (note 2, note 3) bus free time t buf 4700 ns time between start and stop conditions. fast mode (400 khz) clock frequency t scl 0 400 khz clock high time t high 600 ns clock low time t low 1300 ns sda and scl rise time t r 20 + 0.1c b 300 ns from v il to v ih (note 1) sda and scl fall time t f 20 + 0.1c b 300 ns from v ih to v il (note 1) start condition hold time t hd:sta 600 ns after this period, the first clock pulse is generated repeated start condition setup time t su:sta 600 ns only relevant for repeated start condition data hold time t hd:dat 0 900 ns (note 4) data input setup time t su:dat 100 ns stop condition setup time t su:sto 600 ns output valid from clock t aa 0 1200 ns (note 2, note 3) bus free time t buf 1300 ns time between start and stop conditions. input filter spike suppression t sp 0 50 ns sda and scl pins (note 5) note 1: this parameter is ensured by characterization and not 100% tested. 2: this specification is not a part of the i 2 c specification. this spec ification is equivalent to the data hold time ( t hd:dat ) plus sda fall (or rise) time: t aa = t hd:dat + t f ( or t r ). 3: if this parameter is too short, it can create an unintended star t or stop condition to other dev ices on the bus line. if this parameter is too long, clock low time (t low ) can be affected. 4: for data input: this parameter must be longer than t sp . if this parameter is too long, the data input setup (t su:dat ) or clock low time (t low ) can be affected. for data output: this parameter is charac terized, and tested indirectly by testing t aa parameter. 5: this parameter is ensured by characterization and not 100% tested. this parameter is not available for standard mode. downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 27 mcp3426/7/8 high speed mode (3.4 mhz) clock frequency f scl 03 . 4m h z c b = 100 pf 01 . 7m h z c b = 400 pf clock high time t high 60 ns c b = 100 pf, f scl = 3.4 mhz 120 ns c b = 400 pf, f scl = 1.7 mhz clock low time t low 160 ns c b = 100 pf, f scl = 3.4 mhz 320 ns c b = 400 pf, f scl = 1.7 mhz scl rise time (note 1) t r 40 ns from v il to v ih , c b = 100 pf, f scl = 3.4 mhz 80 ns from v il to v ih , c b = 400 pf, f scl = 1.7 mhz scl fall time (note 1) t f 40 ns from v ih to v il , c b = 100 pf, f scl = 3.4 mhz 80 ns from v ih to v il , c b = 400 pf, f scl = 1.7 mhz sda rise time (note 1) t r: dat 80 ns from v il to v ih , c b = 100 pf, f scl = 3.4 mhz 160 ns from v il to v ih , c b = 400 pf, f scl = 1.7 mhz sda fall time (note 1) t f: data 80 ns from v ih to v il , c b = 100 pf, f scl = 3.4 mhz 160 ns from v ih to v il , c b = 400 pf, f scl = 1.7 mhz data hold time (note 4) t hd:dat 0 70 ns c b = 100 pf, f scl = 3.4 mhz 0 150 ns c b = 400 pf, f scl = 1.7 mhz output valid from clock (notes 2 and 3) t aa 150 ns c b = 100 pf, f scl = 3.4 mhz 310 ns c b = 400 pf, f scl = 1.7 mhz start condition hold time t hd:sta 160 ns after this period, the first clock pulse is generated repeated start condition setup time t su:sta 160 ns only relevant for repeated start condition data input setup time t su:dat 10 ns stop condition setup time t su:sto 160 ns input filter spike suppression t sp 0 10 ns sda and scl pins (note 5) table 5-5: i 2 c serial timing specifications (continued) electrical specifications: unless otherwise specified, all limits are specified for t a = -40 to +85c, v dd = +2.7v to +5.0v, v ss = 0v, chn+ = chn- = v ref /2. parameters sym min typ max units conditions note 1: this parameter is ensured by characterization and not 100% tested. 2: this specification is not a part of the i 2 c specification. this spec ification is equivalent to the data hold time ( t hd:dat ) plus sda fall (or rise) time: t aa = t hd:dat + t f ( or t r ). 3: if this parameter is too short, it can create an unintended star t or stop condition to other dev ices on the bus line. if this parameter is too long, clock low time (t low ) can be affected. 4: for data input: this parameter must be longer than t sp . if this parameter is too long, the data input setup (t su:dat ) or clock low time (t low ) can be affected. for data output: this parameter is charac terized, and tested indirectly by testing t aa parameter. 5: this parameter is ensured by characterization and not 100% tested. this parameter is not available for standard mode. downloaded from: http:/// mcp3426/7/8 ds22226a-page 28 ? 2009 microchip technology inc. figure 5-7: i 2 c bus timing data. t f scl sda t su:sta t sp t hd:sta t low t high t hd:dat t aa t su:dat t r t su:sto t buf 0.7v dd 0.3v dd downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 29 mcp3426/7/8 6.0 basic application configuration the mcp3426/7/8 devices can be used for various precision analog-to-digital converter applications. these devices operate with very simple connections to the application circuit. the following sections discuss the examples of the de vice connections and applications. 6.1 connecting to the application circuits 6.1.1 bypass capacitors on v dd pin for an accurate measurement, the application circuit needs a clean supply voltage and must block any noise signal to the mcp3426/7/8 devices. figure 6-1 shows an example of using two bypass capacitors (a 10 f tantalum capacitor and a 0.1 f ceramic capacitor) on the v dd line of the mcp3428. these capacitors are helpful to filter out any hi gh frequency noises on the v dd line and also provide the momentary bursts of extra currents when the device needs from the supply. these capacitors should be placed as close to the v dd pin as possible (within one inch). if the application circuit has separate digital and analog power supplies, the v dd and v ss of the mcp3426/7/8 devices should reside on the analog plane. 6.1.2 connecting to i 2 c bus using pull-up resistors the scl and sda pins of the mcp3426/7/8 are open-drain configurations. these pins require a pull-up resistor as shown in figure 6-1 . the value of these pull-up resistors depends on the operating speed (standard, fast, and high speed) and loading capacitance of the i 2 c bus line. higher value of pull-up resistor consumes less power, but increases the signal transition time (higher rc time constant) on the bus. therefore, it can limit th e bus operating speed. the lower value of resistor, on the other hand, consumes higher power, but allows higher operating speed. if the bus line has higher capacitance due to long bus line or high number of devices con nected to the bus, a smaller pull-up resistor is needed to compensate the long rc time constant. the pull-up resistor is typically chosen between 5 k and 10 k ranges for standard and fast modes, and less than 1 k for high speed mode depending on the presence of bus loading capacitance. 6.1.3 i 2 c address selection pins (mcp3427 and mcp3428) the user can tie the adr0 and adr1 pins to v ss , v dd , or left floating. see more details in section 5.3.2 device address bits (a2, a1, a0) and address selection pins (mcp3427 and mcp3428) . figure 6-1: typical connection. figure 6-2 shows an example of multiple device connections. the i 2 c bus loading capacitance increases as the number of device connected to the i 2 c bus line increases. the bus loading capacitance affects on the bus operating speed. for example, the highest bus operating speed for the 400 pf bus capacitance is 1.7 mhz, and 3.4 mhz for 100 pf. therefore, the user needs to consider the relationship between the maximum operation speed versus. the number of i 2 c devices that are connected to the i 2 c bus line. figure 6-2: example of multiple device connection on i 2 c bus. r p v dd 45 6 9 ch2- v ss ch3+ adr1 adr0 3 12 ch2+ ch3- 2 13 ch1- ch4+ 1 14 ch1+ ch4- 7 8 sda scl v dd mcp3428 1110 c 1 c 2 input input signal 2 signal 1 input input signal 4 signal 3 t o mcu (master) r p i 2 c address selection pins rp is the pull-up resistor: 5k - 10 k for f scl = 100 khz to 400 khz ~700 for f scl = 3.45 mhz c 1 : 0.1 f, ceramic capacitor c 2 : 10 f, tantalum capacitor sda scl microcontroller mcp3426 mcp3428 (pic16f876) mcp4725 mcp3427 downloaded from: http:/// mcp3426/7/8 ds22226a-page 30 ? 2009 microchip technology inc. 6.1.4 device connection test the user can test the pres ence of the mcp3426/7/8 on the i 2 c bus line without performing an input data conversion. this test can be achieved by checking an acknowledge response from the mcp3426/7/8 after sending a read or write command. here is an example using figure 6-3 : a. set the r/w bit high in the address byte. b. check the ack pulse after sending the address byte. if the device acknowledges (ack = 0 ), then the device is connected, otherwise it is not connected. c. send stop or start bit. figure 6-3: i 2 c bus connection test. 6.1.5 differential and single-ended configuration figure 6-4 shows typical connection examples for differential and single-ended inputs. differential input signals can be connected to the chn+ and chn- input pins, where n = the channel number (1, 2, 3, or 4). for the single-ended input, the input signal is applied to one of the input pins (typically connected to the chn+ pin) while the other input pin (typically chn- pin) is grounded. all device characteristics hold for the single-ended configuration, but this configuration loses one bit resolution because the input can only stand in positive half scale. refer to section 1.0 electrical characteristics . figure 6-4: differential and single-ended input connections. 123456789 scl sda 1 1 0 1a2a1a0 1 start bit address byte address bits device bits r/w stop bit mcp342x ack response (a) differential input signal connection: chn+ chn- mcp342x input signal (b) single-ended input signal connection: chn+ chn- mcp342x input signal sensor sensor excitation excitation r 1 r 2 downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 31 mcp3426/7/8 6.2 application examples the mcp3426/7/8 devices can be used for broad ranges of sensor and data acquisition applications. figure 6-5 shows a circuit example measuring both the battery voltage and current using the mcp3426 device. channels 1 and 2 are measuring the voltage and the current, respectively. when the input voltage is greater than the internal reference voltage (v ref = 2.048v), it needs a voltage divider circuit to prevent the output code from being saturated. in the example, r 1 and r 2 form a voltage divider. the r 1 and r 2 are set to yield v in to be less than the internal reference voltage (v ref = 2.048v). for the current measurement, the device measure the voltage across the current sensor, and converts it by dividing the measured voltage by a known resistance value. the voltage drops across the sensor is waste. therefore, the current m easurement often prefers to use a current sensor with smaller resistance value, which, in turn, requires high resolution adc device. the device can measure the input voltage as low as 7.8 v range (or current in ~ a range) with 16 bit resolution and pga = 8 settings. the msb (= sign bit) of the output code determines the direction of the current, which identifies the charging or the discharging current. figure 6-5: battery voltage and charging/discharging current measurement. 5k v dd v ss 0.1 f 10 f t o mcu (master) scl sda 5k ch2+ scl ch2- r 1 r 2 battery (rechargeable) 23 4 5 6 7 ch1- sda 1 8 ch1+ v dd current sensor to load to battery discharging current charging current r 1 and r 2 = voltage divider v in r 2 r 1 r 2 + ------------------ v bat = v in mcp3426 v bat downloaded from: http:/// mcp3426/7/8 ds22226a-page 32 ? 2009 microchip technology inc. figure 6-6 , shows an example of using the mcp3428 for four-channel thermocouple temperature measurement applications. figure 6-6: four-channel thermocouple applications. with type k thermocouple, it can measure temperature from 0c to +1250c degrees. the full scale output range of the type k thermocouple is about 50 mv. this provides 40 v/c (= 50 mv/ 1250c) of measurement resolution. equation 6-1 shows the measurement budget for sensor signal using the mcp3426/7/8 device wit h 16 bits and pga = 8 settings. with this configuration, the mcp3428 can detect the input signal level as low as approximately 7.8 v. by setting the internal pga option to x8, the 40 v/c input from the t hermocouple is amplified internally to 320 v/c before the conversion takes place. this results in about 5 lsb output codes per 1c of change in temperat ure, with 16-bit conversion mode. equation 6-1: 5k v dd 45 6 9 ch2- v ss ch3+ 3 12 ch2+ ch3- 2 13 ch1- ch4+ 1 14 ch1+ ch4- 7 8 sda scl v dd mcp3428 1110 0.1 f 10 f t o mcu (master) mcp9800 mcp9800 mcp9800 mcp9800 isothermal block isothermal block thermocouple sensor heat scl sda sda scl sda scl v dd sda scl sda scl adr1adr0 5k input signal level after gain of 8: where: 1 lsb = 62.5 v with 16 bit configuration detectable input signal level 62.5 v/pga = 7.8125 v for pga 8 = = 40 v/c () 8 320 v/c = ? = no. of lsb/c 320 v/c 62.5 v ------------------------ - 5.12 codes/c == downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 33 mcp3426/7/8 equation 6-2 shows an example of calculating the expected number of output code with various pga gain settings for type k thermocouple output. equation 6-2: expected number of output code for type k thermocouple figure 6-7: example of pressure and temperature measurement. log 2 50 mv 62.5 v pga ----------------- - ------------------ ?? ?? ?? ?? = 9.6 bits for pga = 1 = 10.6 bits for pga = 2 = 11.6 bits for pga = 4 = 12.6 bits for pga = 8 expected number of output code = where: 1 lsb = 62.5 v with 16 bit configuration. 800 pga ? () ln 2 () ln ------------------------------------- ?? ?? = 5k v dd 45 6 9 ch2-v ss ch3+ adr1adr0 3 12 ch2+ ch3- 2 13 ch1- ch4+ 1 14 ch1+ ch4- 7 8 sda scl v dd mcp3428 11 10 0.1 f 10 f t o mcu (master) 5k v dd thermistor v dd pressure sensor v dd v dd v dd r 1 r 2 thermistor r 2 r 1 r 1 and r 2 = voltage divider v in r 2 r 1 r 2 + ------------------ v dd = (npp301) pressure sensor (npp301) v in v in downloaded from: http:/// mcp3426/7/8 ds22226a-page 34 ? 2009 microchip technology inc. figure 6-7 shows an example of measuring both pressure and temperature. the pressure is measured by using npp 301 (manufactured by ge novasensor), and temperature is measured by a thermistor. the pressure sensor output is 20 mv/v. this gives 100 mv of full scale output for v dd of 5v (sensor excitation voltage). equation 6-3 shows an example of calculating the number of output code for the full scale output of the npp301. equation 6-3: expec ted number of output code for npp301 pressure sensor the thermistor temperatur e sensor can measure the temperature range from -100c to +300c. the resistance of the thermistor sensor decreases as temperature increases (negative temperature coefficient). as shown in figure 6-7 , the thermistor (r 2 ) forms a voltage divider with r 1 . the thermistor sensor is si mple to use and widely used for the temperature measurem ent applications. it has both linear and non-linear responses over temperature range. r 1 is used to adjust the linear region of interest for measurement. expected log 2 100 mv 62.5 v pga ----------------- - -------------------- - ?? ?? ?? ?? = 10.6 bits for pga = 1 = 11.6 bits for pga = 2 = 12.6 bits for pga = 4 = 13.6 bits for pga = 8 number of output code = where: 1 lsb = 62.5 v with 16 bit configuration. 1600 pga ? () ln 2 () ln ---------------------------------------- ?? ?? = downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 35 mcp3426/7/8 7.0 packaging information 7.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e xxxxxxxx xxxxyyww nnn 8-lead soic (300 mil) (mcp3426) 3426a0 e sn^^0945 256 8-lead msop (mcp3426) example : xxxxxx ywwnnn 3426a0 945256 3 e 8-lead dfn (2x3) (mcp3426) example: xxxyww nn abx945 25 example: downloaded from: http:/// mcp3426/7/8 ds22226a-page 36 ? 2009 microchip technology inc. package marking information (continued) 14-lead soic (150 mil) (mcp3428) example: xxxxxxxxxxx yywwnnn xxxxxxxxxxx mcp3428 0945256 xxxxxxxx nnn yyww 14-lead tssop (4.4 mm) (mcp3428) example: mcp3428 e 256 0945 e/sl^^ 3 e 12 3 4 56 7 8 9 10 10-lead dfn (3x3) (mcp3427) 10-lead msop (mcp3427) example: xxxxxxywwnnn 3427e 945256 example: xxxx yyww nnn 12 3 4 56 7 8 9 10 34270945 256 downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 37 mcp3426/7/8 !""#$%& ' ! " #$ %! & '(!%&! %( % ")%% % " * & & # "% ( % " + * ) ! % " & "% ,- . /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! ' 2% & %! % * " ) ' % * $ % % " % %% 133))) & &3 * 4% 55,, & 5&% 6 67 8 6!&( $ 6 9 % ./0 7 : % 9 % "$$ . 0% %* + ,2 7 5 % /0 7 ;"% , + /0 ,# " "5 % + < .. ,# " ";"% , . < . 0% %;"% ( . + 0% %5 % 5 + . 0% % % ,# " " = < < d n e note 1 1 2 exposed pad note 1 2 1 d2 k l e2 n e b a3 a1 a note 2 bottom view top view ) 0 +0 downloaded from: http:/// mcp3426/7/8 ds22226a-page 38 ? 2009 microchip technology inc. !""#$%& ' 2% & %! % * " ) ' % * $ % % " % %% 133))) & &3 * downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 39 mcp3426/7/8 ()" * + )%)* & ' ! " #$ %! & '(!%&! %( % ")%% % " & ", "%!" &"$ %! "$ %! % # " .&& " + & "% ,- . /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! 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' 2% & %! % * " ) ' % * $ % % " % %% 133))) & &3 * 4% 55,, & 5&% 6 67 8 6!&( $ 6 % ./0 7 : % 9 % "$$ . 0% %* + ,2 7 5 % + /0 ,# " "5 % +. 9 7 ;"% , + /0 ,# " ";"% , .9 . 0% %;"% ( 9 . + 0% %5 % 5 + . 0% % % ,# " " = < < d n note 1 1 2 e b e n l e2 note 1 1 2 d2 k exposed pad bottom view top view a3 a1 a note 2 ) 0 >+/ downloaded from: http:/// mcp3426/7/8 ds22226a-page 44 ? 2009 microchip technology inc. . !""#$%& ' 2% & %! % * " ) ' % * $ % % " % %% 133))) & &3 * downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 45 mcp3426/7/8 . ()" * + /%)* & ' ! " #$ %! & '(!%&! %( % ")%% % " & ", "%!" &"$ %! "$ %! % # " .&& " + & "% ,- . /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! ' 2% & %! % * " ) ' % * $ % % " % %% 133))) & &3 * 4% 55,, & 5&% 6 67 8 6!&( $ 6 % ./0 7 : % < < " " * * . 9. . % "$$ < . 7 ;"% , /0 " " * ;"% , + /0 7 5 % + /0 2%5 % 5 > 9 2% % 5 .,2 2% ? < 9? 5 "* 9 < + 5 ";"% ( . < ++ d e e1 n note 1 1 2 b e a a1 a2 c l l1 ) 0 / downloaded from: http:/// mcp3426/7/8 ds22226a-page 46 ? 2009 microchip technology inc. .0 )" * +)((, ! ""#$%)*-& ' ! " #$ %! & '(!%&! %( % ")%% % " @ $ %0 % % + & ", "%!" &"$ %! "$ %! % # " .&& " & "% ,- . /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! ' 2% & %! % * " ) ' % * $ % % " % %% 133))) & &3 * 4% 55,, & 5&% 6 67 8 6!&( $ 6 % /0 7 : % < < . " " * * . < < % "$$@ < . 7 ;"% , > /0 " " * ;"% , + /0 7 5 % 9 >./0 0 &$ a % b . < . 2%5 % 5 < 2% % 5 ,2 2% ? < 9? 5 "* < . 5 ";"% ( + < . " $% .? < .? " $% /%%& .? < .? note 1 n d e e1 1 23 b e a a1 a2 l l1 c h h ) 0 >./ downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 47 mcp3426/7/8 ' 2% & %! % * " ) ' % * $ % % " % %% 133))) & &3 * downloaded from: http:/// mcp3426/7/8 ds22226a-page 48 ? 2009 microchip technology inc. .0 12 +)2( +)" * +)10 0""#$%1))* & ' ! " #$ %! & '(!%&! %( % ")%% % " & ", "%!" &"$ %! "$ %! % # " .&& " + & "% ,- . /01 / & % # % ! ))%!%% ,21 $ & '! ! )%!%% '$$& % ! ' 2% & %! % * " ) ' % * $ % % " % %% 133))) & &3 * 4% 55,, & 5&% 6 67 8 6!&( $ 6 % >./0 7 : % < < " " * * 9 . % "$$ . < . 7 ;"% , > /0 " " * ;"% , + . " " * 5 % . . 2%5 % 5 . > . 2% % 5 ,2 2% ? < 9? 5 "* < 5 ";"% ( < + note 1 d n e e1 1 2 e b c a a1 a2 l1 l ) 0 9/ downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 49 mcp3426/7/8 noe: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// mcp3426/7/8 ds22226a-page 50 ? 2009 microchip technology inc. notes: downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 51 mcp3426/7/8 appendix a: revision history revision a (december 2009) original release of this document. downloaded from: http:/// mcp3426/7/8 ds22226a-page 52 ? 2009 microchip technology inc. notes: downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 53 mcp3426/7/8 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: mcp3426: 2-channel 16-bit adc mcp3426t: 2-channel 16-bit adc (tape and reel) mcp3427: 2-channel 16-bit adc mcp3427t: 2-channel 16-bit adc (tape and reel) mcp3428: 4-channel 16-bit adc mcp3428t: 4-channel 16-bit adc (tape and reel) temperature range: e = -40c to +125c package: mc = plastic dual flat, no lead (2x3 dfn), 8-lead ms = plastic micro small outline (msop), 8-lead sn = plastic small outline soic, 8-lead mf = plastic dual flat, no lead (3x3 dfn) 10-lead un = plastic micro small outline (msop), 10-lead sl = plastic small outline soic (150 mil body), 14-lead st = plastic tssop (4.4mm body), 14-lead part no. -x /xx package temperature range device examples: a) mcp3426a0-e/mc: 2-channel adc, 8ld dfn package. b) mcp3426a0t-e/mc: tape and reel, 2-channel adc, 8ld dfn package. c) mcp3426a0-e/ms: 2-channel adc, 8ld msop package. d) mcp3426a0t-e/ms: tape and reel, 2-channel adc, 8ld msop package. e) mcp3426a0-e/sn: 2-channel adc, 8ld soic package. f) mcp3426a0t-e/sn: tape and reel, 2-channel adc, 8ld soic package. a) mcp3427-e/mf: 2-channel adc, 10ld dfn package. b) mcp3427t-e/mf: tape and reel, 2-channel adc, 10ld dfn package. c) mcp3427-e/un: 2-channel adc, 10ld msop package. d) mcp3427t-e/un: tape and reel, 2-channel adc, 10ld msop package. a) mcp3428-e/sl: 4-channel adc, 14ld soic package. b) mcp3428t-e/sl: tape and reel, 4-channel adc, 14ld soic package. c) mcp3428-e/st: 4-channel adc, 14ld tssop package. d) mcp3428t-e/st: tape and reel, 4-channel adc, 14ld tssop package. downloaded from: http:/// mcp3426/7/8 ds22226a-page 54 ? 2009 microchip technology inc. notes: downloaded from: http:/// ? 2009 microchip technology inc. ds22226a-page 55 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are register ed trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, pic 32 logo, real ice, rflab, select mode, total endurance, tsharc, uniwindr iver, wiperlock and zena are trademarks of microchip te chnology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2009, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:/// ds22226a-page 56 ? 2009 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4080 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-6578-300 fax: 886-3-6578-370 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 03/26/09 downloaded from: http:/// |
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